#1楼主：Sun UltraSPARC II处理器 (即日开源)
文章发表于：2008-07-29 09:34
Sun UltraSPARC II处理器
SPARC，全称为“可扩充处理器架构”（Scalable Processor ARChitecture），是RISC微处理器架构之一。它最早于1985年由升阳电脑所设计，也是SPARC国际公司的注册商标之一。这家公司于1989年成立，其目的是向外界推广SPARC，以及为该架构进行符合性测试。此外该公司为了扩阔SPARC设计的生态系统，SPARC国际也把标准开放，并授权予多间生产商采用，包括德州仪器、Cypress半导体、富士通等。由于SPARC架构也对外完全开放，因此也出现了完全开放原始码的LEON处理器，这款处理器以VHDL语言写成，并采用LGPL授权。
SPARC架构原设计给工作站使用，及后应用在升阳、富士通等制造的大型SMP服务器上。而升阳开发的Solaris操作系统也是为SPARC设计的系统之一，除Solaris外，NeXTSTEP、Linux、FreeBSD、OpenBSD及NetBSD系统也提供SPARC版本。
现时最新版本的SPARC为第8及第9版，在2005年12月，升阳方面宣布其UltraSPARC T1处理器将采用开放原始码方式。
开源CPU--OpenSparc T1简介 FPGA级别
2006年3月，Sun宣布开源化其多核心UltraSparc T1 CPU的处理器设计，采用的是GNU通用公共许可证(GNU GPL license)。之前Sun已经公开了"Hypervisor"API规范，允许各公司将Linux、BSD 及其他操作系统移植到UltraSparc T1平台。
Sun是业界首家将复杂的硬件设计使用GNU GPL许可进行发布的公司，而此举也将为UltraSparc T1处理器增加曝光度，并吸引开发人员为该平台开发软硬件解决方案。
该硬件设计的开源发布包括64-bit UltraSparc T1的Verilog硬件描述语言源代码，验证套装和模拟模型，ISA规范及Solaris 10 OS虚拟镜像。T1处理器的代号为“Niagara”，于去年发布并应用于Sun的T1000/T2000服务器中。 Sun目前推出了4、6、8核心的CPU版本，且每核心最多支持4线程，即总共最多32线程。T1基于Sparc V9架构，每核心集成16KB指令缓存和8KB主数据缓存，整个处理器共享3MB L2缓存。“OpenSparc T1”芯片设计，验证套装，架构和性能模型工具已经发布在http://www.opensparc.net网站。Sun还发布了“Cool Tools”，其中包括优化多线程CPU性能的各种程序以及CMT编程及描绘工具。
OpenSparc T1处理器的主要特征包括：
8个Sparc V9处理核心，每核心4线程，共计32线程
每处理核心16KB一级指令缓存，共128KB；
每处理核心8KB一级数据缓存，共64KB；
3MB二级缓存，4-way bank，12向关联，各核心共享；
4个DDR2内存控制器，每通道位宽144bit，总带宽峰值25GB/s；
IEEE754兼容浮点单元(FPU)，各核心共享；
J-Bus输入输出接口，峰值带宽2.56GB/s，128bit多元地址/数据复用总线。
图示是OpenSPARC T1方框图
光盘为OpenSparc的源代码（FPGA），内涵相关技术资料及开发工具。以OpenSparc T1资源为主兼有部分OpenSparc T2文档。
··········
SPARC架构的技术资料，但由于OpenSPARC是业界唯一复杂计算计算机芯片的开源项目。
#2
文章发表于：2008-07-31 11:31
拿到设计资料 最近的日期08年6月19号。最近开始搭建设计环境
Solaris 10 （建个虚拟环境）GCC4.2 设计文档写的相当完美。
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
1 Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Navigating UltraSPARC Architecture 2007 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Fonts and Notational Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Implementation Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Notation for Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.3 Informational Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Reporting Errors in this Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 The UltraSPARC Architecture 2007 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.2 Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.2.1 Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.2.2 Register Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.3 System Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.3.1 Binary Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.3.2 UltraSPARC Architecture 2007 MMU . . . . . . . . . . . . . . 24
3.1.3.3 Privileged Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.4 Architectural Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.5 UltraSPARC Architecture 2007 Compliance with SPARC V9
Architecture 25
3.1.6 Implementation Compliance with UltraSPARC Architecture 2007
25
3.2 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.1 Integer Unit (IU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.2 Floating-Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
#4
文章发表于：2008-08-08 08:02
OpenSPARC.net is the genesis of a vision by engineers, technologists, evangelists, and executives at Sun Microsystems, Inc. to create a larger community where open conversations and collaborative development projects spawn dramatic innovations around chip design. Individual programmers as well as representatives from Universities, industry associations, supporting software companies, foundries, entrepreneurs, large corporations and visionaries have already begun to participate in this expanded community.
SPARC stands for Scalable Processor ARchitecture. The technology is based on pioneering research around RISC at the University of California, Berkeley. It has been the basis of Sun's premiere line of servers since its introduction the Sun 4/260 and 4/280, in mid-1987 and then as the Campus-1 "pizza box" in 1989. That year, Sun transferred the ownership of the SPARC specifications to SPARC International, who continues to license the technology and manage compliance testing for the trademark today. SPARC has had a long history of openness. Take a look at Dawn of OpenSPARC.
Goals of the OpenSPARC Initiative
- To significantly increase participation in processor architecture development and application design by making cutting-edge hardware intellectual property freely available.
- To eliminate barriers to the next big build-out of the Internet.
- To improve collaboration and cooperation among hardware designers.
- To enable community members to build on proven technology at a markedly lower cost.
- To encourage innovation.
- To foster bringing bold new products to market.
What OpenSPARC Means to You
- As a developer
Opening the UltraSPARC T1 & UltraSPARC T2 source code lets developers create innovative software applications faster, and with a higher degree of hardware integration than ever before. Software developers will now be able to create highly optimized applications that are tightly integrated with the hardware, creating unique, high-value solutions for specific markets.
- As a customer
Opening the UltraSPARC T1 & UltraSPARC T2 source code helps create an environment that will speed the development of new, thread-rich applications. Customers will enjoy more choices and shorter development cycles.
- As an OEM
Opening the UltraSPARC T1 & UltraSPARC T2 source code gives OEMs the opportunity to create unique solutions built on a proven architecture. OEM's can apply their expertise in hardware design to create new, high-value solutions for specific customers and markets rapidly.
- As a foundry or silicon provider
A 64-bit, Chip Multi-threaded (CMT), SPARC architecture design point is now freely available for innovation and quick productization.
- As a student or professor in academia
A modern, real (not "toy") design -- OpenSPARC can boot real off-the-shelf commercial operating systems (e.g.Solaris, Linux, FreeBSD). Use a real design for your study or research.
Join us - take part in new synergies that take place, and contribute to new solutions as they unfold. Help us stretch existing technology into the next generation. The more time and energy you have to interact with opensparc.net community members, the more exposure you'll gain among your peers. The return investment can come in a variety of ways, including the reputation you or your organization earn through leadership roles and contributions to the site and, perhaps more importantly, the market pulse and community needs you discover and leverage.
Testimonials
See what people have said about OpenSPARC.
Get involved
There are many different ways that individuals, companies, universities, existing communities, and other organizations can become involved in OpenSPARC.net.
Spread the Word
It's time to open doors to collaboration around chip design. Help spread the word OpenSPARC.net is a home for making this happen.
- Link your site to OpenSPARC.net.
- List your product or service in our community marketplace.
- "Talk" with your peers by joining a mailing list or forums.
- Submit an article using our contact form and we'll consider posting it on our site.
- Please forward any suggestions for content you might have to: using our contact form. Features in opensparc.net are not limited to traditional articles. They can be code reviews, summaries of interesting conversations, or repurposed presentations, forums, or polls.
Learn from the real chip
Explore the code that works. Learn techniques that have been tested to create low-power, highly productive chips.
Contribute to a new real chip
Take the code, implement your ideas, and propose a new design. Today's UltraSPARC solution is just the beginning....
- Float your ideas
Join the announcement and/or the general mailing list. Or if you're interested in a particularly project, join the project mailing list. Write a blog related to opensparc and send an email to:
blog@opensparc.net
This e-mail address is being protected from spam bots, you need JavaScript enabled to view it
to request your page to be listed.
- Post your notes
If you are studying chip design at a university or research lab, and you have some interesting notes, post them to the forums, post them to the wiki and/or submit them to the University Page by using our contact form.
- Contribute your code
If you have some code - either binary or source - that others can use, submit your contribution to the Cool Tools project. Remember, you must provide a license for the code and agree to the Terms of Participation. If your contribution includes source code, you must also sign a Contributor Agreement.
- Join a project
Take a look our projects and join one.
- Start a project
Do you have project already started or an idea for one that is related/connected to OpenSPARC, then we have a place where we can host it for you. Take a look at Starting a project.
- Contribute to the OpenSPARC Book Project
We are in the process of developing an open book on the OpenSPARC T1. The intention of this open book is to assist the OpenSPARC development community by describing the OpenSPARC T1 in detail. We have an outline started, but we need more contributors. Join the OpenSPARC book project: http://wiki.opensparc.net.
- Share your Course Material
Collaborate and share course material related to OpenSPARC, chip multi-threading, multi-core in many areas including hardware design, design tools, CMT Architecture, software systems design, operating systems, concurrent computing and other related areas. We're looking for professors who have a passion for teaching and contributing to their field of study by sharing their course material with others. Take a look at site we are developing and the course materials already available: http://wiki.opensparc.net/bin/view.pl/CourseMaterial.
#5
文章发表于：2008-08-08 08:03
This chapter is starting with resources and commentary on EDA tools as well as additional pointers to IP needed for the implementation of OpenSPARC RTL.
If You Are New to EDA, please refer back to the OpenSPARC web-site over here: http://www.opensparc.net/eda.html
However, if you have done a thing or two using CAD/EDA tools, perhaps there's something I can add to explore further
- Let's take the prototyping aspects. While some of you may want to use FPGA, there are vendors (see www.dac.com
for some of the FPGA vendors) who are coming up with 'stackable' boards of high density, high capacity
FPGAs. With such boards, you can implement very large designs including system components/ASICs. One such vendor
claimed capacities of 'as large a system as you want' when talking to their representative at an expo.
- If, however, you have decided to implement it into a foundry (a chip fabrication facility) provided ASIC or SoC? , then you
have even more options to consider. Usually, these foundaries will provide design services, where they can provide foundry specific
services using their own certified EDA tool chain, including RTL to logic implementation, or logic to physical implementation
or even packaging, and providing fully tested parts. Almost every large foundry in the world has these
'certified' tool-chain and tool usage methodology that work with the foundry specific process. These often include
pre-characterized and pre-silicon verified standard libraries, memory compilers and even standardized IOs.
Some components are also available as "hard IP", for example standard IO drivers for memories or high speed
serial ports.
- Of course, there's always the last, most customised option, Customer-Owned-Tooling, or COTs for short,
where you, as a designer team, buy your own implementation tools, except those for mask-making and fabrication.
As the process features get smaller than the wavelengths of light, more and more fabless semiconductor
design houses, who are designing chips at the high-end of the spectrum for a given process,
tend to own their own EDA tools. Including, of course, Sun, when designing OpenSPARC T1.
- Along with the sheer complexity of nanometer technologies the tooling techniques reache new thresholds.
Tools used for 180 nanometer technology would just fail at 65 nanometer.
- Costs scale up significantly, specially with the industry standard commercial tools. After all, who can
do a design of 100s of millions of transistors without EDA tools?
Aah, won't this be a prime ground for open source? I believe that OpenSPARC would help trigger
more and more open sourcing of EDA tools as the community collaboration picks up.
- Certainly, almost all large commercial organizations as well as universities already have some business
arrangements with the top vendors, but more often then not, there is limited usage available. And, given
the pace of process technology changes, EDA tools start to get obsolete quickly.
- Take, for example, logic synthesis. There are probably only 3 or 4 vendors who have credible, high
capacity and silicon-proven synthesis tools. When combined with physical synthesis (logic synthesis
that is also aware of physical constraints like distances, routing congestions, etc.), the solutions are
even fewer. Add to this any features that help to manage the complexity of processes that have
large variability in the physical structures (even within one chip), and you'll need a whole new class
of capabilities, generally referred to as 'DFx' or Design for Manufacturing/Yield/Variability/etc.
#7
文章发表于：2008-08-23 10:50
在线注册，获得授权，就可以下载。环境还得自己搭建/