#1楼主：加一和减一的VHDL代码

文章发表于：2008-01-24 11:41

以下为加一和减一的VHDL代码

library ieee;
   
use ieee.std_logic_1164.all;

entity exer1 is
    port ( a   :in std_logic := '0';
           b   :in std_logic := '0';
           clk :in std_logic;
           c   :inout integer range -100 to 100 := 0);
end entity;

architecture bhv of exer1 is
signal temp : integer range -100 to 100 := 0;
begin
    process (clk,a, b)
       begin
          if clk'event and clk='1' then
           if a = '1' then
             temp <= c + 1;    
          elsif b = '1' then
             temp <= c - 1;
        end if;
    end if;
    end process;
      c<= temp;

end bhv;