zh-cnGoodspeed Rss2Sat, 06 Dec 2008 01:30:59 GMTTue, 27 May 2008 19:49:00 GMThttp://group.ednchina.com/265/10695.aspx程序的功能挺简单的，就显示三个数字（三位数），数字能增减这样 两个底层VHDL写的文件都编译通过了，连成顶层的编译就出现错误 Error:TRI or OPNDRN buffer'.....':can only drive logic if connected to a BIDIR pin 程序见附http://group.ednchina.com/265/10695.aspxwkg_0072Thu, 24 Jan 2008 11:41:00 GMThttp://group.ednchina.com/265/8000.aspx以下为加一和减一的VHDL代码library ieee; use ieee.std_logic_1164.all;entity exer1 is port ( a :in std_logic := '0'; b :in std_logic := '0'; clk :in std_logic; c :http://group.ednchina.com/265/8000.aspxxuhaowen