#1楼主：SOPC系统高级示例

文章发表于：2008-03-19 06:02

In Figure 1.1, the Nios® II processor accesses the control and status
registers of on-chip components using an Avalon-MM interface. The
scatter gather DMAs send and receive data using Avalon-ST interfaces.
Four components include interrupt interfaces that are serviced by
software running on the Nios II processor. A PLL accepts a clock via a
clock sink interface and provides two clock sources. Finally, two
components include conduit interfaces to access off-chip resources.

In Figure 1.2, an external processor accesses the control and status
registers of on-chip components via an external bus bridge with an
Avalon-MM interface. The PCI Express root port controls the printed
circuit board and the other components of the FPGA by driving an
on-chip PCI Express endpoint with an Avalon-MM master interface. Five
components include interrupts that are handled by the external processor.
As in Figure 1.1, a PLL accepts a reference clock via a clock sink interface
and provides two clock sources. Finally, the flash and SRAM memories
use an Avalon-MM tristate interface to share FPGA pins.