帮忙把这个问题分析下 -- FPGA讨论组 -- EDN电子设计技术

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#1楼主：帮忙把这个问题分析下

文章发表于：2008-05-08 01:07

这是我写verilog程序

// Module Declaration
module clock_generater
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
clk, rst, alu_clk, fetch, clk1
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input clk;
input rst;
output alu_clk;
output fetch;
output clk1;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

reg /*clk2,clk4,*/fetch,alu_clk;
reg [7:0] state;
wire clk/*,rst*/;

parameter s1=8'b00000001,
    s2=8'b00000010,
   s3=8'b00000100,
   s4=8'b00001000,
   s5=8'b00010000,
   s6=8'b00100000,
   s7=8'b01000000,
   s8=8'b10000000,
    idle="8"'b00000000;
/*
assign clk1=~clk;
always @ (negedge clk)
   if(rst)
   begin
   clk2<=0;
   clk4<=1;
   fetch<=0;
   alu_clk<=0;
   state<=idle;
   end
  else
   begin
    case(state)
     s1:
      begin
      clk2<=~clk2;
      alu_clk<=~alu_clk;
      state<=s2;
      end
     s2:
      begin
      clk2<=~clk2;
      clk4<=~clk4;
      alu_clk<=~alu_clk;
      state<=s3;
      end
     s3:
      begin
      clk2<=~clk2;
      state<=s4;
      end
     s4:
      begin
      clk2<=~clk2;
      clk4<=~clk4;
      fetch<=~fetch;
      state<=s5;
      end
     s5:
      begin
      clk2<=~clk2;
      state<=s6;
      end
     s6:
      begin
      clk2<=~clk2;
      clk4<=~clk4;
      state<=s7;
      end
     s7:
      begin
      clk2<=~clk2;
      state<=s8;
      end
     s8:
      begin
      clk2<=~clk2;
      clk4<=~clk4;
      fetch<=~fetch;
      state<=s1;
      end
      idle: state<=s1;
    default:state<=idle;
   endcase
  end
endmodule
*/
assign clk1=~clk;
always @ (posedge clk)
if(rst)
  begin
   fetch<=0;
   alu_clk<=0;
   state<=idle;
  end
else
  begin
  case (state)
   s1:
    begin
    alu_clk<=~alu_clk;
    state<=s2;
    end
   s2:
    begin
    alu_clk<=~alu_clk;
    state<=s3;
    end
   s3: state<=s4;
   s4:
    begin
    fetch<=~fetch;
    state<=s5;
    end
   s5: state<=s6;
   s6: state<=s7;
   s7: state<=s8;
   s8:
    begin
    fetch<=~fetch;
    state<=s1;
    end
  idle: state<=s1;
  default:state<=idle;
  endcase
  end
endmodule
想得到的时序图请看附件